1 REM Ins{nd av Hans Holmberg <2838> 1987-06-11 02.09.30 (DUMP) Utdrag ur Z80 Assembly Language Programming by Lance A.Leventhal Z80 SIO Write and read registers: ================================= Write registers: The Z80 SIO contains eight registers in each channel that are programmed (written into) by the system software to configure the functional personality of each channel. All Write registers, with the exception of Write Register 0, require two bytes to be properly programmed. The first byte contains three bits that point to the selected register (D0-D2); the second byte is the actual control word that is being written to that register to configure the SIO. Write Register 0 is a special case. RESET (either internal command or external input) will initialize the SIO to Write Register 0. Contained in the first byte of any Write register access are the basic commands (CMD2-CMD0) and the CRC controls (CRC0,CRC1) so that maximum system controll and flexibility is maintained. Write Register 0 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! +--+--+--+--+--+--+--+--+ ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 0 0 0 Register 0 ! ! ! ! ! 0 0 1 Register 1 ! ! ! ! ! 0 1 0 Register 2 ! ! ! ! ! 0 1 1 Register 3 ! ! ! ! ! 1 0 0 Register 4 ! ! ! ! ! 1 0 1 Register 5 ! ! ! ! ! 1 1 0 Register 6 ! ! ! ! ! 1 1 1 Register 7 ! ! 0 0 0 Null Code ! ! 0 0 1 Send Abort (SDLC) ! ! 0 1 0 Reset Extarnal or Status Interrupts ! ! 0 1 1 Channel Reset ! ! 1 0 0 Reset Rx Interrupt on First Character ! ! 1 0 1 Reset Tx Interrupt Pending ! ! 1 1 0 Error Reset ! ! 1 1 1 Return from Interrupt (Ch-A Only) 0 0 Null Code 0 1 Reset Rx CRC Checker 1 0 Reset Tx CRC Generator 1 1 Reset CRC/SYNCS Sent/Sending Latch Write Register 1 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! +--+--+--+--+--+--+--+--+ ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! +-> External Interrupt Enable ! ! ! ! ! ! +----> Tx Interrupt Enable ! ! ! ! ! +-------> Status Affects Vector (Ch-B Only) ! ! ! 0 0 Rx Interrupt Disable ! ! ! 0 1 Rx Interrupt on First Character Only or Error ! ! ! 1 0 Int. on All Rx Chars. (Parity Affects Vector) ! ! ! 1 1 Int. on All Rx Chars. (Parity dont Affect Vector) ! ! +----------------> WAIT/READY on R/T ! +-------------------> WAIT FN/READY FN +----------------------> WAIT/READY Enable Write Register 2 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! --> Contains Interrupt Vector +--+--+--+--+--+--+--+--+ Write Register 3 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! +--+--+--+--+--+--+--+--+ ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! +-> Rx Enable ! ! ! ! ! ! +----> SYNC Character Load Inhibit ! ! ! ! ! +-------> Adress Search Mode (SDLC) ! ! ! ! +----------> Rx CRC Enable ! ! ! +-------------> Enter Hunt Mode ! ! +----------------> Auto Enables 0 0 Rx 5 Bits/Character 0 1 Rx 6 Bits/Character 1 0 Rx 7 Bits/Character 1 1 Rx 8 Bits/Character Write Register 4 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! +--+--+--+--+--+--+--+--+ ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! +-> Parity Enable ! ! ! ! ! ! +----> Parity Even/Odd (Odd active Low) ! ! ! ! 0 0 SYNC Modes Enable ! ! ! ! 0 1 1 Stop Bit/Character ! ! ! ! 1 0 1.5 Stop Bit/Character ! ! ! ! 1 1 2 Stop Bits/Character ! ! 0 0 8 Bit SYNC Character ! ! 0 1 16 Bite SYNC Charcter ! ! 1 0 SDLC Mode (01111110 SYNC Flag) ! ! 1 1 External SYNC Mode 0 0 x1 Clock Mode 0 1 x16 Clock Mode 1 0 x32 Clock Mode 1 1 x64 Clock Mode Write Register 5 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! +--+--+--+--+--+--+--+--+ ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! +-> Tx CRC Enable ! ! ! ! ! ! +----> RTS ! ! ! ! ! +-------> SDLC/CRC-16 ! ! ! ! +----------> Tx Enable ! ! ! +-------------> Send BREAK ! 0 0 Tx 5 Bits (or Less)/Character ! 0 1 Tx 6 Bits/Character ! 1 0 Tx 7 Bits/Character ! 1 1 Tx 8 Bits/Character +----------------------> DTR Write Register 6 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! --> SYNC Bits 0-7 (Also SDLC Adress Field) +--+--+--+--+--+--+--+--+ Write Register 7 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! --> SYNC Bits 8-15 (For SDLC It must be programmed +--+--+--+--+--+--+--+--+ to "01111110" for Flag Recognition) Read Registers: The Z80 SIO contains three registers that can be read to obtain the status of each channel. Status information includes error conditions, interrupt vector, and standard communication interface protocol signals. To read the contents of a selected Read register, the system software must first write out to the SIO the byte containing the pointer information (D0-D2) in exactly the same manner as a Write register operation. Then, by issuing a READ operation, the contents of the adressed Read/Status register can be read by the Z80 CPU. The real power in this type of command structure is that the programmer has complete freedom, after pointing to the selected register, of either reading or writing to initialize or test that register. By designing software to initialize the Z80 SIO in a modular, structured fashion, the programmer can use the powerful Z80 Block I/O instructions to significantly simplify and speed his software development and debug. Read Register 0 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! +--+--+--+--+--+--+--+--+ ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! +-> Rx Character Available ! ! ! ! ! ! +----> Interrupt Pending (Ch-A Only) ! ! ! ! ! +-------> Tx Buffer Empty ! ! ! ! +----------> DCD ! ! ! +-------------> SYNC/HUNT ! ! +----------------> CTS ! +-------------------> Sending CRC/SYNCS +----------------------> BREAK/ABORT Read Register 1 +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! +--+--+--+--+--+--+--+--+ ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! +-> All Sent ! ! ! ! ! ! ! Residue Data for 8 Rx Bits/Character Programmed: ! ! ! ! ! ! ! ================================================ ! ! ! ! ! ! ! I-Field Bits I-Field Bits in ! ! ! ! ! ! ! in Previous Second Previous ! ! ! ! ! ! ! Byte Byte ! ! ! ! ! ! ! ------------ --------------- ! ! ! ! 1 0 0 0 3 ! ! ! ! 0 1 0 0 4 ! ! ! ! 1 1 0 0 5 ! ! ! ! 0 0 1 0 6 ! ! ! ! 1 0 1 0 7 ! ! ! ! 0 1 1 0 8 ! ! ! ! 1 1 1 1 8 ! ! ! ! 0 0 0 2 8 ! ! ! +-------------> Parity Error (Special Rx Cond. Interrupts) ! ! +----------------> Rx Overrun Error - " - ! +-------------------> CRC/Framing Error - " - +----------------------> End of Frame (SDLC) - " - Read Register 2 (Channel B Only) +--+--+--+--+--+--+--+--+ !D7!D6!D5!D4!D3!D2!D1!D0! --> Contains Interrupt Vector +--+--+--+--+--+--+--+--+ ----------------------------------------------------------------------------- Sammanst{llt av Hans Holmerg <2838> /Mummel'87